The field of the disclosure relates generally to power switching module assemblies and, more particularly, to power switching module assembly internal bus structures that provide low circuit inductance.
At least some known semiconductor power switching device packages route signals either on a power substrate or through metal traces in a wall geometry. For the power substrate, the signal paths are typically direct bond or active metal brazed copper or aluminum on a ceramic substrate which are single layer and require that the traces be adjacent to one another on a planar surface. The semiconductor devices are then wire bonded to the planar metal traces which run across the module and are wire bonded to the output terminals.
These known packages have typically tried to address higher operating frequencies and lower inductance packages solely with internal layout routing on a direct-bond-copper (DBC) substrate or within the side walls of the package. This includes an optimization of a length and a width of the metal traces and an orientation of the semiconductor devices. For some of the newer designs, planar bus bars have been used primarily in an orientation orthogonal to the DBC substrate with small tabs for making connection to the DBC surface. Although these constructions provide improvements, they are primarily geared toward reducing the number of wire bonds and improving manufacturing efficiency for standard silicon products. As more wide band gap semiconductors become available, the operation frequency and voltage levels continue to rise making parasitic packaging effects even more important. Wirebondless technologies such as thermal spray technologies, power overlay, and silver diffusion sintering joints may facilitate eliminating wire bonds and creating more planar interconnects, although most of these attempts require changes to the standard footprint either mechanically, electrically, or both to demonstrate the effect.